1. Field of the Invention
The present invention relates to implementation of point-to-point port protocols such as AGP (Accelerated Graphics Port) in a computer, and more particularly, to hardware improvements which may contribute to improvements in systems based on these protocols and to increasing applicable fields thereof.
2. Description of the Background Art
The Accelerated Graphics port standard is proposed by Intel Corporation and is defined as a point-point port protocol, i.e., only one single AGP device is allowed to be connected to the AGP slot on the motherboard of a PC (Personal Computer). The device according to this AGP standard (AGP device) is used to execute 3D/2D (three dimensional/two dimensional) graphics processings or the like, and AGP devices have been recently in great demand in the field of personal computers.
Since the AGP standard is however defined as a point-to-point port protocol, the following problem has arisen. Referring to FIG. 43, for example, if a conventional motherboard 600 used in a personal computer has only one AGP slot 610, only one add-in board (AIB) 602 including an AGP device 612 can be mounted in this AGP slot 610 as a matter of course. As a result, an additional AGP device of the same type as AGP device 612 cannot be readily provided.
If a motherboard 620 has an AGP slot 630 and a PCI slot 632 as shown in FIG. 44, add-in board 602 can be mounted to AGP slot 630 and another add-in board 624 having a PCI device 642 or the like can be mounted to PCI slot 632.
However, there are two major applications that require to connect multiple devices to the AGP port. First, graphics board vendor would like to connect two or more of their rendering controller (RC) to the single AGP slot, either to increase fill rate or to enable multiple display support. The conventional configuration shown in FIG. 43 or FIG. 44 cannot answer the need.
Secondly, in the example shown in FIG. 44, two slots, AGP slot 630 and PCI slot 632, are provided at motherboard 620, and both slots must be used. Since a great many peripheral devices are provided as add-in boards today, the number of necessary slots must be as small as possible. It is therefore preferable to enable both capabilities implemented by AGP devices and by PCI devices to the motherboard using for example only a single slot.
An example would be Video Editing Boards that, in addition to video editing capabilities (via PCI devices) also offer 3D/2D capabilities as a single board solution. Such capabilities correspond to the functions of a so-called bridge, but there exists no such bridge that provides combinations in such a wide range as described above.
Furthermore, if a circuit to offer a special function such as a core for geometrical operation is provided on a bridge, the bridge can provide combinations of capabilities in a wider range, but again there has been no such bridge.
It is therefore an object of the present invention to provide a bridge device which can provide various functional devices including AGP device using a single slot.
Another object of the present invention is to provide a bridge device which can provide various functional devices including AGP devices and a special core circuit using a single slot.
A bridge device according to a first invention includes first port connected to a first bus, and a plurality of second ports respectively connected to a plurality of second buses, the first port includes a master module and a slave module according to a first protocol and a master module according to a second protocol, and the second protocol is a point to point port protocol, each of the second ports includes a master module and a slave module according to the first protocol and a slave module according to the second protocol. The bridge device further includes a plurality of first-in-first-out memories forming asynchronous data paths between the first port and the plurality of second ports and an arbitrator for arbitrating between transactions in a contention generated in the data paths formed by the first-in-first-out memories based on the protocols related to the transactions.
Since the data paths are formed between the first port and the plurality of second ports, and a contention between transactions can be resolved based on the protocol used, a plurality of devices can be connected using a single slot of a motherboard. As a result, while preventing the number of slots used in the motherboard from increasing, a plurality of devices of the same kind can be connected to expand the processing capability or a plurality of devices of different kinds can be connected to provide various kinds of capabilities.
Preferably, each of the modules adds to a transaction request an attribute representing a protocol and a data rate related to the transaction, and each of the first-in-first-out memories includes storage for storing a transaction and attribute storage memory for storing an attribute corresponding to each transaction. The bridge device further includes programmable transformer for executing protocol or data rate transformation performed based on an attribute stored by the attribute storage for each of the data path.
This bridge device executes protocol or data rate transformation for transactions, and thus various combinations of devices and hosts can be achieved.
More preferably, the first protocol is a PCI protocol, and the second protocol is an AGP protocol, the plurality of first-in-first-out memories include a first first-in-first-out memory forming a data path to each of the plurality of second ports from the first port.
The AGP device is essentially adapted to communicate with the host on a one-to-one basis only and cannot be functionally expanded in an easy manner, but since the AGP devices can be connected to the plurality of secondary ports, the function and the processing capabilities can be easily expanded.
Further preferably, the first first-in-first-out memory includes a plurality of memory banks each having an input coupled to the first port and an output coupled to each of the plurality of second ports and a plurality of queues provided corresponding to the plurality of second ports, and each of the plurality of queues holds information to specify a memory bank storing data directed to a corresponding one of the second ports.
The first first-in-first-out memory must correctly direct data to the plurality of secondary ports. Data to any of the secondary ports is stored in a common memory bank, and data directed to each of the secondary ports is managed by the queue. The circuit scale can be reduced as compared to providing sets of memory banks for respective destinations.
According to a further aspect of the present invention, the first first-in-first-out memory further includes a receiving circuit which receives data broadcast from the first port to the plurality of second ports, storing duplicates in a number corresponding to that of the plurality of second ports in the memory banks, and supplying information to specify a corresponding bank storing the data to be broadcast to each of the plurality of queues for storage.
Since the data is duplicated and stored in the plurality of memory banks, and information to specify the memory banks is input in the queues for the plurality of secondary ports, the same data can be transmitted to any of the secondary ports. More specifically, data can be readily broadcast using the first-in-first-out memory.
Preferably, the bridge device according to a seventh invention further includes an SBA unit for applying an SBA request issued as a sideband signal from the plurality of second ports to the first port, the second first-in-first-out memory includes a plurality of memory banks each having an input connected to the plurality of second ports and an output connected to the first port for storing transaction data output from the plurality of second ports, an AGP queue for maintaining information to specify a memory bank storing data corresponding to an AGP request issued from the plurality of second ports within the queue and a PCI queue for maintaining information to specify a memory bank storing PCI transaction data issued from the second ports within the queue, and the first port includes a circuit for taking data from a memory bank specified by information read out from a head entry of the AGP queue or PCI queue depending upon the kind of data to be read out.
If a plurality of kinds of requests are present, the order of data is managed separately by corresponding queue (the AGP queue and the PCI queue), so that data can be read out in a correct order for each of the kinds.
More preferably, the first port further includes a module for direct memory access, and the SBA unit includes an arbitrating circuit for arbitrating between an SBA request from the plurality of second ports and an SBA request from the module for direct memory access for application to the first port.
Since SBA requests from three sources are arbitrated and applied to the first port, direct memory access and transactions between the resources connected to the plurality of second ports and the first memory can be smoothly processed.
More preferably, the bridge device further includes an operation core to execute a prescribed operation processing. The plurality of first-in-first-out memories form asynchronous data paths between the operation core and the first port and the plurality of second ports in addition to the asynchronous data paths between the first port and the plurality of second ports.
Since the operation core is incorporated in the bridge device, a larger number of combinations of functions can be readily implemented. In addition, if an operation core for a particular purpose is incorporated in the bridge device, the system can be expanded less costly as compared to the use of a plurality of add-in boards.
In accordance with another aspect of the present invention, a bridge device includes: a first port connected to a first bus; a plurality of second ports connected to a plurality of second buses; a plurality of first-in-first-out memories for forming asynchronous data paths between the first port and the plurality of second ports; and an arbitrating circuit for arbitrating contentions caused on the data paths formed by the plurality of first-in-first-out memories. The arbitrating circuit arbitrates the contentions based on protocols associated with respective transactions. The first port has a module that gives a command for initiating a data transaction to a first device connected to the first bus, or receives a command for initiating a data transaction from the first device. Each of the plurality of second ports has a module that gives a command for initiating a data transaction to a second device connected to corresponding one of the second ports, or receives a command for initiating a data transaction from the second device.